Підсилювач постійного струму

Abstract

The direct current amplifier comprises three current sources, the first and the second input transistors, the first and the second output transistors, a neutral bus, an additional and a negative power buses, a resistor, a balancing capacitor, twenty two transistors, input and output buses with input bus being united with emitters of the first and the second input transistors and the first contact of the first resistor, and with the first contact of the balancing capacitor. Bases of the first and the second input transistors are connected with bases and collectors of the first and the second transistors accordingly and with terminals of the first and the second current sources. Emitters of the first and the second transistors are integrated and connected with neutral bus. The second terminals of the first and the second current sources are connected with additional and negative buses accordingly, collectors of the first and the second input transistors are connected with collectors of the third and the fourth transistors accordingly and with bases of the seventh and the eighth transistors accordingly. Bases of the third and the fourth transistors are connected with bases and collectors the ninth and the tenth transistors accordingly and with collectors of the fifth and the sixth transistors accordingly. Collectors of the third and the ninth transistors are connected with additional power bus. Collectors of the fourth and the tenth transistors are connected with negative bus, emitters of the fifth and the sixth transistors are united, emitters of the seventh and the eighth transistors are connected with collectors of the thirteenth and fourteenth transistors accordingly and with bases of the seventeenth and eighteenth transistors accordingly and also with the first and the second terminals of the third current source. Bases of the thirteenth and fourteenth transistors are connected with bases and collectors of fifteenth and sixteenth transistors accordingly and with emitters of the seventeenth and the eighteenth transistors accordingly. Emitters of the fourteenth and fifteenth transistors are connected with additional power bus. Emitters of the fourteenth and sixteenth transistors are united with negative power bus. Collectors of the seventeenth and the eighteenth transistors are united with bases and collectors of eleventh and twelfth transistors accordingly, and also with bases of the first and the second output transistors accordingly. Emitters of the eleventh and the twelfth transistors are integrated and connected with the second balancing capacitor contact. Collectors the first and the second output transistors and connected with additional and negative buses accordingly. Emitters of the first and the second output transistors are integrated and connected with the first resistor second contact and also with output bus. The fifth and the sixth transistor bases are connected with bases and collectors of the eleventh and twelfth transistors accordingly and with collectors of the seventeenth and the eighteenth transistors accordingly.