Пристрій для швидкого дійсного перетворення Хартлі-Фур'є

Abstract

The proposed device for fast real-time discrete Hartley-Fourier processing contains a timing unit, a read-only memory, two address counters, two input data registers, an intermediate register, an output data register, three switches, two data multipliers, a summing-subtracting unit, and random-access memory. The proposed device is supplemented with the third and the fifth switches. The information inputs of these switches are connected to the corresponding outputs of the input data registers, the information outputs are connected to the corresponding inputs of the data multipliers, and the control inputs are connected to the output of the timing unit.