Методи та пристрої оцінювання бітових помилок у промислових комп’ютерних системах

Abstract

The thesis presents the results of research to improve the accuracy estimation of parameters bit errors (PBE) on the background of single additive errors. Position method of evaluation lengths and positions insertions/deletions bits fall out that, unlike the existing ones, based on a calculation of the difference in the two positions synchrosymbol reference and adopted pseudo-recursive sequences can increase the accuracy of PBE assessment against the background of single additive errors. Method rearrangement relative position synchrosymbols by the frequency of their occurrence, which, unlike the existing ones, involves a rearrangement of elements of the queue at any one time, only on the basis of the input and output elements allows using consistent implementation of computational processes to increase the accuracy of the evaluation PBE and provides less hardware complexity device, built on the basis of positional method. The development of these methods allows almost order to reduce hardware complexity endpoints detection and estimation of parameters bit errors. Improved correlation method of parallel processing coefficients of cross-correlation, which, unlike the existing ones, based on the use of pyramidal convolution coefficients cross correlation, making it possible to increase the accuracy of estimation of bit errors and speed required to find parameters of bit errors in real time with high-resolution ability. Based on the proposed methods algorithms, flow diagrams device estimation of parameters bit errors and their software implementation in industrial computer systems.