Обчислювальний пристрій

Abstract

The proposed computing device contains two pulse counters, a binary code comparator, an OR logic element, an AND logic element, a monostable multivibrator, and additionally, an adder-subtractor. The counting input of the first counter is connected to the output of the AND logic element, and the outputs are connected to the corresponding inputs of the first group of the inputs of the binary code comparator. The inputs of the second group of the inputs of the binary code comparator are connected with the corresponding outputs of the second counter, and the output is connected to the first input of the OR logic element. The second input of the OR logic element is connected via the monostable multivibrator to the input of the device that is designed for entering a pulse-time-modulated signal and the first input of the AND logic element. The adder-subtractor contains n groups of AND logic elements, with n elements in each group, and two groups of OR logic elements, with (n-1) elements in each group. The first input of the i-th element of each j-th group of the AND logic elements (і = 1,n; j = 1,n) is connected to the seventh input of the first group of the inputs of the adder-subtractor, and the second input is connected to the j-th input of the second group of the second group of the inputs of the adder-subtractor. The output of the first element of the first group of the AND logic elements is connected to the n-bit output for the difference code of the adder-subtractor. The output of the n-th element of the first group of the AND logic elements is connected to the 1-bit output for the sum code of the adder-subtractor.