Моделі форсуючих сигналів для прискореного порозрядного аналого-цифрового перетворення з ваговою надлишковістю

Abstract

The article is dedicated to models of forcing signals for fast bitwise analog A D conversion with weight superfluity. Using of the signals allows accelerating considerably balancing process due to com pensation of dynamic errors. The models of forcing signals for surplus positional notation of (0, 1) and (1,-1) types are examined. The equations that were obtained are common as for common surplus positional notation and for weight superfluity based on binary sets