Вхідний комплементарний підсилювальний каскад із самобалансуванням

Abstract

An input self-equalizing complementary amplification stage relates to pulse technique and may be used in analogue-to-digital converters and digital instruments. Zero buses, fifth, sixth, seventh and eighth transistors, as well as new circuit connections are incorporated to the proposed input complimentary amplification stage. First and second current sources and third, fourth, fifth, seventh, eighth transistors form DC mode setting circuit of self-equalizing complementary amplification stage built using first and second transistors correspondingly. Due to the proposed device linearity is increased and scale error is eliminated. Increase of linearity is obtained due to automation of balancing process of coefficients for amplified currents through upper and low amplification channels which built on first and second transistors of different conductivity. Eliminated of scale error is obtained due to distribution of input signal in equal parts to buses of first and second transistors of different conductivity.