Паралельний аналого-цифровий перетворювач

Abstract

The proposed parallel analog-to-digital converter contains comparators for the high-order bits of digital code, a parallel analog-to-digital converter for the low-order bits of digital code, bit memory cells, an AND-OR logic element, a controlled voltage source, a reference voltage source, a code converter, an analog switching unit, and a timing unit. The outputs of the analog-to-digital converter for the low-order bits of digital code are connected to the signal inputs of the corresponding memory cells. The outputs of the comparators are connected to the signal inputs of the corresponding memory cells via the AND-OR logic element. The outputs of the memory cells are connected to the corresponding outputs of the proposed converter. The first inputs of the comparators and the signal inputs of the analog-to-digital converter for the low-order bits of digital code are connected to the input of the controlled voltage source. The second inputs of the comparators are connected to the output of the reference voltage source. The inputs of the code converter are connected to the outputs of the comparators, and the outputs are connected to the corresponding control inputs of the analog switching unit. The signal inputs of the analog switching unit are connected to the output of the reference voltage source. The timing inputs of the analog-to-digital converter for the low-order bits of digital code and the memory cells are connected to the output of the timing unit.