Метод аналізу тривалості виконання програмного коду з урахуванням архітектури мікроконтролера

Abstract

The paper deals with common problems that are likely to be encountered when analyzing the execution time of the firmware of any typical embedded system. The overview of the existing approaches performed by the authors has revealed that methods based on analysis of the cash memory and the instruction pipeline architecture of the embedded system being investigated are impractical for evaluating the execution time of the firmware running in microcontroller-based embedded systems. One of the ways of making the results of firmware execution time analysis more accurate is to take into consideration the internal architecture of the microcontroller including delays introduced by data exchange between internal blocks of the microcontroller via modules that implement standard communication interfaces.

We have proposed a method for firmware execution time analysis that assumes the following steps: determining the settings of the microcontroller on the basis of the firmware, determining interconnections between the synchronization buses and the internal blocks, analysis of the settings of communication interfaces for external peripheral devices, and calculation of the firmware execution time itself. Upon the performed multiple numerical experiments, one can conclude that the proposed method provides more accurate results in comparison with the existing methods.

The authors are planning to enhance the accuracy of calculating the firmware execution time due to making allowances for the duration of reading data from random access memory and due to the fact that the proposed method might be automated, in order to reduce the time of analysis for commercial projects. After being automated, the introduced method is applicable for verification of different methods for measurement of the firmware execution time.