Mathematical model of glitches in DAC with weight redundancy

Abstract

Glitches appear in digital-to-analog converters and lead to significant limitations of conversion accuracy and speed, which is critical for DAC and limits their usage, especially in the direct digital synthesis systems. This paper researches the causes, the specificity of the appearance of glitches in DAC and the possibility of using weight redundancy in order to reduce glitches in DAC. There had been suggested and analyzed the mathematical model of glitches in DAC with weight redundancy. There had also been proved that glitch amplitude is significantly influenced by the value of the voltage control of the DAC and the parasitic capacities of the digital keys. There had been shown that the attenuation time (duration) of the glitch is significantly influenced by the value of load resistance. The paper shows the expediency of using the DAC based on redundant positional number systems including Fibonacci p-codes. The simulation results prove that with the increase of the parameter p, the characteristics of glitch are significantly improved in comparison with the classical binary system, namely the amplitude and the attenuation time of glitch decrease.