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dc.contributor.authorZakharchenko, S.en
dc.contributor.authorHumeniuk, R.en
dc.contributor.authorЗахарченко, С. М.uk
dc.contributor.authorГуменюк, Р. С.uk
dc.date.accessioned2021-11-16T10:18:57Z
dc.date.available2021-11-16T10:18:57Z
dc.date.issued2020
dc.identifier.citationZakharchenko S. Bit error notification and estimation in redundant successive-approximation ADC [Electronic resource] / S. Zakharchenko, R. Humeniuk // Informatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska, Vol. 10, № 4. – 2020. – P. 29-32. – Access mode: https://ph.pollub.pl/index.php/iapgos/article/view/2225.en
dc.identifier.urihttp://ir.lib.vntu.edu.ua//handle/123456789/34082
dc.description.abstractThe article is devoted to research on the possibilities to use redundant number systems for bit error notification in a successive-approximation ADC during the main conversion mode. The transfer function of a successive-approximation ADC with a non-binary radix is analyzed. If the radix is less than 2, not all possible code combinations appear on the converter output. The process of formation of unused combinations is investigated. The relationship between the bit`s deviations and the list of unused combinations is established. The possibilities of estimating the bit error value without interrupting the process of analog-to-digital conversion is considered.en
dc.language.isoenen
dc.publisherLublin University of Technologyen
dc.relation.ispartofInformatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska. Vol. 10, № 4 : 29-32.en
dc.subjectsuccessive-approximation ADCen
dc.subjectredundant number systemsen
dc.subjectADC transfer functionen
dc.titleBit error notification and estimation in redundant successive-approximation ADCen
dc.typeArticle


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